VHDL design - D Flip Flop (DFF)

D Flip Flop (DFF) plays a role to save data.
Precisely, DFF only saves input data which is synchronized with clock.
For this reason, DFF is generally used in delaying data.

The structure of DFF is illustrated in Fig.1.

<Fig.1 : Structure of DFF>

It includes reset (RESET), data input (DIN), clock (CLK) and data out (DOUT).
If reset is enable, DOUT has '0' value.
Otherwise, DOUT has DIN value which is synchronized with CLK.
We can describe its operation with VHDL, and its source code is given by

Library IEEE;use ieee.std_logic_1164.all;entity DFF is port(  RESET : in std_logic;  CLK : in std_logic;  DIN : in std_logic;  DOUT : out std_logic);end DFF;architecture rtl of DFF isbeginprocess(RESET,CLK,DIN)begin  if RESET = '1' then    DOUT <= '0';  elsif CLK'event and CLK = '1' then    DOUT <= DIN;  end if;end process;end rtl;

Its output wave stream is shown in Fig. 2.

<Fig.2 : output wave of DFF>

In this case, I use 'rising edge' of clock and set the RESET signal as '1' (i.e., reset is enabled when RESET = '1').
We can confirm that the output signal is delayed in one clock.

This is basic DFF VHDL code.
But if we use this source code in practical circuit, the system may be operated very slowly.
Why?

The answer will be in next post. lol.